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240pin DDR3 SDRAM VLP Registered DIMM
DDR3 SDRAM VLP Registered DIMM Based on 2Gb A version
HMT325V7AFR8C HMT351V7AFR8C HMT351V7AFR4C HMT41GV7AMR8C HMT41GV7AMR4C
** Contents may be changed at any time without any notice.
Rev. 0.02 / Apr. 2009
1
Revision History
Revision No. 0.01 0.02 History Initial Release Added IDD Specificaion Draft Date 2009-04 2009-04 Remark
Rev. 0.02 / Apr. 2009
2
Table of Contents
1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 2GB, 256Mx72 Module(1Rank of x8) 3.2 4GB, 512Mx72 Module(2Rank of x8) 3.3 4GB, 512Mx72 Module(1Rank of x4) 3.4 8GB, 1Gx72 Module(4Rank of x8) 3.5 8GB, 1Gx72 Module(2Rank of x4) 4. Input/Output Capacitance & AC Parametrics 5. IDD Specifications 6. DIMM Outline Diagram 6.1 2GB, 256Mx72 Module(1Rank of x8) 6.2 4GB, 512Mx72 Module(2Rank of x8) 6.3 4GB, 512Mx72 Module(1Rank of x4) 6.4 8GB, 1Gx72 Module(4Rank of x8) 6.5 8GB, 1Gx72 Module(2Rank of x4)
Rev. 0.02 / Apr. 2009
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1. Description
This Hynix DDR3 VLP (Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 2Gb A generation. These are intended for use as main memory in server and workstation systems, providing a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
* VDD=VDDQ=1.5V * VDDSPD=3.3V to 3.6V * Fully differential clock inputs (CK, CK) operation * Differential Data Strobe (DQS, DQS) * On chip DLL align DQ, DQS and /DQS transition with CK transition * DM masks write data-in at the both rising and falling edges of the data strobe * All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock * Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported * Programmable additive latency 0, CL-1, and CL-2 sup ported * Programmable CAS Write latency (CWL) = 5, 6, 7, 8 * Programmable burst length 4/8 with both nibble sequential and interleave mode * BL switch on the fly * 8banks * 8K refresh cycles /64ms * DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8) with support balls * Driver strength selected by EMRS * Dynamic On Die Termination supported * Asynchronous RESET pin supported * ZQ calibration supported * TDQS (Termination Data Strobe) supported (x8 only) * Write Levelization supported * Auto Self Refresh supported * 8 bit pre-fetch * SPD with Integrated TS of Class B
1.1.2 Ordering Information
Organizatio n 256Mx72 512Mx72 512Mx72 1Gx72 1Gx72 # of DRAMs 9 18 18 36 36 # of ranks 1 2 1 4 2
Part Name HMT325V7AFR8C-G7/H9 HMT351V7AFR8C-G7/H9 HMT351V7AFR4C-G7/H9 HMT41GV7AMR8C-G7/H9 HMT41GV7AMR4C-G7/H9
Density 2GB 4GB 4GB 8GB 8GB
Materials Halogen free Halogen free Halogen free Halogen free Halogen free
FDHS X X X O O
*Please Contact local sales administrator for more details of part number
Rev. 0.02 / Apr. 2009 4
1.2 Speed Grade & Key Parameters
MT/S Grade tCK (min) CAS Latency tRCD (min) tRP (min) tRAS (min) tRC (min) CL-tRCD-tRP DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 Unit -H9 1.5 9 13.5 13.5 36 49.5 9-9-9 ns tCK ns ns ns ns tCK
1.3 Address Table
2GB(1Rx8) Organization Refresh Method Row Address Column Address Bank Address Page Size # of Rank # of Device 256M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 1 9 4GB(2Rx8) 512M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2 18 4GB(1Rx4) 512M x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 1 18 8GB(4Rx8) 1G x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 4 36 8GB(2Rx4) 1G x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 2 36
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2. Pin Architecture
2.1 Pin Definition
Pin Name A0-A9,A11 A13-A15 BA0-BA2 RAS CAS WE S0-S3 CKE0-CKE1 ODT0-ODT1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0-DQS8 Description Address Inputs SDRAM Bank Addresses Row Address Strobe Column Address Strobe Write Enable Chip Selects Clock Enables On-die termination Inputs Data Input/Output Data Check Bits Input/Output Data Strobes Data Strobes, Negative Line Num -ber 14 3 1 1 1 4 2 2 64 8 9 9 9 Pin Name A10/AP A12/BC SCL SDA SA0-SA2 Par_in ERR_OUT EVENT TEST RESET VDD VSS VREFDQ VREFCA VTT 9 1 1 VDDSPD CK1 CK1 Description Address Input/Autoprecharge Address Input/Autoprecharge Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs Parity Bit For The Address and Control Bus Parity Error Found on the Address and Control Bus Reserved for Optional Hardware temperature Sensing Memory Bus Test Tool (Not Connected and Not Usable on DIMMs) Register and SDRAM control pin Power Supply Ground Reference Voltage for DQ Reference Voltage for CA Termination Voltage SPD Power Clock Input, positive line Clock Input, negative line Num -ber 1 1 1 1 3 1 1 1 1 1 22 59 1 1 4 1 1 1
Data Masks DM0-DM8 DQS9-DQS17 Data Strobes TDQS9-TDQS17 Termination Data Strobes DQS9-DQS17 Data Strobes, Negative Line TDQS9-TDQS17 Termination Data Strobes CK0 CK0 Clock Input, positive line Clock Input, positive Line
Rev. 0.02 / Apr. 2009
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2.2 Input/Output Functional Description
Symbol CK0 CK0 CK1 CK1 Type IN IN IN IN Polarity Positive Line Negative Line Function Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver. Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.
Positive Line Terminated but not used on RDIMMs Negative Line Terminated but not used on RDIMMs CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the command decoders for the associated rank of SDRAM when low and disables decoders.When decoders are disabled, new commands are ignored and previous operations continue.Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s).For modules with two registers,S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. On-Die Termination control signals Reference voltage for DQ0-DQ63 and CB0-CB7 Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1. Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. Selects which SDRAM bank of eight is activated. BA0-BA2 define to which bank an Active, Read, Write or Precharge command is being applied.Bank address also determines mode register is to be accessed during an MRS cycle. Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank.A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH).If only one bank is to be precharged, the bank is selected by BA.A12 is also utilized for BL 4/8 identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during Mode Register Set commands. Data and Check Bit Input/Output pins.
CKE0-CKE1
IN
Active High
S0-S3
IN
Active Low
RAS, CAS, WE ODT0-ODT1 VREFDQ VREFCA
IN IN Supply Supply
Active Low Active High
VDDQ
Supply
BA0-BA2
IN
--
A0-A9 A10/AP A11 A12/BC A13-A15
IN
--
DQ0-DQ63, CB0-CB7
I/O
--
Rev. 0.02 / Apr. 2009
7
Symbol DM0-DM8 VDD, VSS VTT DQS0-DQS17 DQS0-DQS17
Type IN Supply Supply I/O I/O
Polarity Active High
Function Masks write data when high, issued concurrently with input data. Power and ground for the DDR3 SDRAM input buffers, and core logic. Termination Voltage for Address/Command/Control/Clock nets.
Positive Edge Positive line of the differential data strobe for input and output data. Negative Edge Negative line of the differential data strobe for input and output data. TDQS/TDQS is applicable for x8 DRAMs only. WHen enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.x4/x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. -- These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board. This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to VDDSPD to act as a pull up. Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. Active Low This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part. The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set to low level (the Clock Driver will remain synchronized with the input clock) Parity bit for the Address and Control bus.("1":Odd, "0":Even) Parity error detected on the Address and Control bus.A resistor may be connected from Err_Out bus line to VDD on the system planar to act as a pull up. Used by memory bus analysis tools (unused (NC) on memory DIMMs)
TDQS9-TDQS17 TDQS9-TDQS17
OUT
SA0-SA2
SDA
I/O
--
SCL
IN
--
VDDSPD
Supply OUT (open drain)
EVENT
RESET
IN
Par_In Err_Out TEST
IN OUT (open drain)
Rev. 0.02 / Apr. 2009
8
2.3 Pin Assignment
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Front Side (left 1-60) VREFDQ VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 Pin # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back Side (right 121-180) VSS DQ4 DQ5 VSS DM0,DQS9,TDQS9 NC, DQS9,TDQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1,DQS10,TDQS10 NC,DQS10,TDQS10 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2,DQS11,TDQS11 NC,DQS11,TDQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3,DQS12,TDQS12 NC, DQS12,TDQS12 Pin # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Front Side (left 61-120) A2 VDD NC, CK1 NC, CK1 VDD VDD VREFCA Par_in, NC VDD A10 / AP BA0 VDD WE CAS VDD S1, NC ODT1, NC VDD S2, NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 Pin # 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 Back Side (right 181-240) A1 VDD VDD CK0 CK0 VDD EVENT, NC A0 VDD BA1 VDD RAS S0 VDD ODT0 A13 VDD S3, NC VSS DQ36 DQ37 VSS DM4,DQS13,TDQS13 NC, DQS13,TDQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5,DQS14,TDQS14 NC, DQS14,TDQS14
NC = No Connect; RFU = Reserved Future Use
Rev. 0.02 / Apr. 2009 9
Pin # 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Front Side (left 1-60) DQS3 VSS DQ26 DQ27 VSS CB0, NC CB1, NC VSS DQS8 DQS8 VSS CB2, NC CB3, NC VSS VTT, NC KEY VTT, NC CKE0 VDD BA2 Err_Out, NC VDD A11 A7 VDD A5 A4 VDD
Pin # 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Back Side (right 121-180) VSS DQ30 DQ31 VSS CB4, NC CB5, NC VSS DM8,DQS17,TDQS17 NC NC,DQS17,TDQS17 VSS CB6, NC CB7, NC VSS NC(TEST) RESET KEY CKE1, NC VDD A15 A14 VDD A12 / BC A9 VDD A8 A6 VDD A3
Pin # 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Front Side (left 61-120) DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT
Pin # 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Back Side (right 181-240) VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6,DQS15,TDQS15 NC, DQS15,TDQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7,DQS16,TDQS16 NC, DQS16,TDQS16 VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT
NC = No Connect; RFU = Reserved Future Use
Rev. 0.02 / Apr. 2009
10
3. Functional Block Diagram
3.1 2GB, 256Mx72 Module(1Rank of x8)
A[N:O]A /BA[N:O]A A[N:O]B /BA[N:O]B ZQ RS0A_n RRASA_n RS0B_n RRASB_n PCK0A_c RCKE0A RCASB_n RCASA_n RWEA_n RODT0A PCK0B_c RCKE0B CK_n CKE CK_n CKE CK_n CKE PCK0A_t RWEB_n PCK0B_t RODT0B ODT ODT
A[N:O]/BA[N:O]
D8
WE_n CK_n CKE CK_t ODT
D4
CAS_n WE_n CK_t
A[O:N]/BA[N:O]
D3
WE_n CK_n CKE CK_t ODT
D5
WE_n CK_t
RAS_n
CAS_n
CS_n
A[O:N]/BA[N:O]
D2
WE_n CK_n CKE CK_t
D6
WE_n CK_t
RAS_n
CAS_n
CS_n
ODT
A[N:O]/BA[N:O]
D1
WE_n CK_n CKE CK_t ODT
D7
WE_n CK_n CKE CK_t ODT
A[N:O]/BA[N:O]
DQS1_t DQS1_c DM1/DQS10_t DQS10_c DQ[15:8]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n CAS_n CS_n
ZQ
DQS7_t DQS7_c DM7/DQS16_t DQS16_c DQ[63:56]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n CAS_n CS_n
A[O:N]/BA[N:O]
ZQ
DQS2_t DQS2_c DM2/DQS11_t DQS11_c DQ[23:16]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0]
ZQ
DQS6_t DQS6_c DM6/DQS15-t DQS15_c DQ[55:48]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n CAS_n CS_n
ODT
A[O:N]/BA[N:O] ZQ
DQS3_t DQS3_c DM3/DQS12_t DQS12_c DQ[31:24]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0]
ZQ
DQS5_t DQS5_c DM5/DQS14_t DQS14_c DQ[47:40]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n CAS_n CS_n
A[O:N]/BA[O:N] ZQ
DQS8_t DQS8_c DM8/DQS17_t DQS17_c CB[7:0]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n CAS_n CS_n
ZQ
DQS4_t DQS4_c DM4/DQS13_t DQS13_c DQ[39:32]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n CS_n
VDDSPD VDD VTT VREFCA VREFDQ VSS
SPD
D0-D8
D0-D8 D0-D8 D0-D8
D0
WE_n CK_n CKE CK_t ODT
A[N:O]/BA[N:O]
DQS _t DQS _c DM /DQS9_t DQS9_c DQ[7:0]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n CAS_n CS_n
ZQ
Vtt
Note:
1.DQ-to-I/O wiring may be changed within byte. 1%.For all other resistor values refer to the 2.ZQ resistors are appropriate wiring diagram.
Vtt
S0_n S1_n BA[N:0] A[N:0] RAS_n CAS_n WE_n CKE0 ODT0 CK0_t CK0_c CK1_t CK1_c PAR_IN
120 1% 120 1%
1: 2 R E G I S T E R / P L L
OERR_n RST_n
RS0A_n CS0_n: SDRAMs D[3:0], D8 RS0BCK_n CS0_n: SDRAMs D[7:4] RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D8 RBA[N:0]B BA[N:0]: SDRAMs D[7:4] RA[N:0]A A[N:0]: SDRAMs D[3:0], D8 RA[N:0]B A[N:0]: SDRAMs D[7:4] RRASA_n RAS_n: SDRAMs D[3:0], D8 RRASB_n RAS_n: SDRAMs D[7:4] RCASA_n CAS_n: SDRAMs D[3:0], D8 RCASB_n CAS_n: SDRAMs D[7:4] RWEA_n WE_n: SDRAMs D[3:0], D8 RWEB_n WE_n: SDRAMs D[7:4] RCKE0A CKE0: SDRAMs D[3:0], D8 RCKE0B CKE0: SDRAMs D[7:4] RODT0A ODT0: SDRAMs D[3:0], D8 RODT0B ODT0: SDRAMs D[7:4] PCK0A_t CK_t: SDRAMs D[3:0], D8 PCK0B_t CK_t: SDRAMs D[7:4] PCK0A_c CK_c: SDRAMs D[3:0], D8 PCK0B_c CK_c: SDRAMs D[7:4] Err_Out_n
VDDSPD EVENT SCL SDA
VDDSPD
SA0
SA0 SA1 SA2 VSS
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
RST_n: SDRAMs D[8:0] S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 120...330
RESET_n
resistor to ground
Rev. 0.02 / Apr. 2009
11
3.2 4GB, 512Mx72 Module(2Rank of x8)
A[N:O]A /BA[N:O]A PCK1A_c RCKE1A RODT1A A[N:O]B /BA[N:O]B RS0A_n RRASA_n RCASA_n PCK0A_c RCKE0A RWEA_n PCK0A_t PCK1A_t RODT0A RODT0B PCK0B RCKE0B RS1A_c RS1B RODT1B
A[O:N]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT
A[N:O]/BA[N:O]
D8
CAS_n WE_n CK_c CKE CK_t ODT
A[N:O]/BA[N:O]
D17
CAS_n WE_n CK_c CKE CK_t ODT
D4
CAS_n WE_n CK_c CKE CK_t ODT
A[N:O]/BA[N:O]
DQS8_t DQS8_c DM8/DQS17_t DQS17_c CB[7:0]
RAS_n
RAS_n
RAS_n
RAS_n
CAS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS4_t DQS4_c DM4/DQS13-t DQS13_c DQ[39:32]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
D13
WE_n WE_n WE_n WE_n CK_c CKE CK_c CKE CK_c CKE CK_c CKE CK_t CK_t CK_t CK_t
A[N:O]/BA[N:O]
D3
CAS_n WE_n CK_c CKE CK_t ODT
A[N:O]/BA[N:O]
D12
CAS_n WE_n CK_c CKE CK_t ODT
D5
CAS_n WE_n CK_c CKE CK_t ODT
A[N:O]/BA[N:O]
DQS3_t DQS3_c DM3/DQS12_t DQS12_c DQ[31:24]
RAS_n
RAS_n
RAS_n
RAS_n
A[N:O]/BA[N:O]
D2
CAS_n WE_n CK_c CKE CK_t ODT
A[N:O]/BA[N:O]
D11
CAS_n WE_n CK_c CKE CK_t ODT
D6
CAS_n WE_n CK_c CKE CK_t ODT
A[N:O]/BA[N:O]
DQS2_t DQS2_c DM2/DQS11_t DQS11_c DQ[23:16]
RAS_n
RAS_n
RAS_n
RAS_n
A[O:N]/BA[N:O]
D1
CAS_n WE_n CK_c CKE CK_t ODT
A[O:N]/BA[N:O]
D10
CAS_n WE_n CK_c CKE CK_t ODT
D7
CAS_n WE_n CK_c CKE CK_t ODT
A[N:O]/BA[N:O]
DQS1_t DQS1_c DM1/DQS10_t DQS10_c DQ[15:8]
RAS_n
RAS_n
RAS_n
RAS_n
A[N:O]/BA[N:O]
D0
CAS_n WE_n CK_c CKE CK_t ODT
D9
CAS_n WE_n CK_c CKE CK_t ODT
A[N:O]/BA[N:O]
DQS0_t DQS0_c DM0/DQS9_t DQS9_c DQ[7:0]
RAS_n
RAS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
Vtt
VDDSPD EVENT_n
Vtt
VDDSPD
CAS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS7_t DQS7_c DM7/DQS16_t DQS16_c DQ[63:56]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
CAS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS6_t DQS6_c DM6/DQS15_t DQS15_c DQ55:48]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
CAS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS5_t DQS5_c DM5/DQS14_t DQS14_ DQ[47:40]
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ
CS_n
D14
D15
D16
SA0
SCL SDA
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
Note: 1. DQ-to-I/O wiring may be changed within a byte. 2. Unless otherwise noted, resistor values are 15 %. 3. ZQ resistors are 240 %. For all other resistor values refer to the appropriate wiring diagram. 4. See the wiring diagrams for all resistors associated with the command, address and control bus.
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
VDDSPD VDD VTT VREFCA VREFDQ VSS
Serial PD
D0-D17 D0-D17 D0-D17 D0-D17 D0-D17
Rev. 0.02 / Apr. 2009
PCK1B RCKE1B
RS0B RRASB
RCASB
PCK0B
RWEB
PCK1B
SA0 SA1 SA2 VSS
12
S0_n S1_n S[3:2] NC BA[N:0] A[N:0] RAS_n CAS_n WE_n CKE0 ODT0
1:2 R E G I S T E R / P L L
RS0A_n RS0B_n
CS0_n: SDRAMs D[3:0], D8 CS0_n: SDRAMs D[7:4]
RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B A[N:0]: SDRAMs D[7:4], D[16:13] RRASA_n RAS_n: SDRAMs D[3:0], D[12:8], D17 RRASB_n RAS_n: SDRAMs D[7:4], D[16:13] RCASA_n CAS_n: SDRAMs D[3:0], D[12:8], D17 RCASB_n CAS_n: SDRAMs D[7:4], D[16:13] RWEA_n WE_n: SDRAMs D[3:0], D[12:8], D17 RWEB_n WE_n: SDRAMs D[7:4], D[16:13] RCKE0A CKE0: SDRAMs D[3:0], D8 RCKE0B CKE0: SDRAMs D[7:4] RODT0A ODT0: SDRAMs D[3:0], D8 RODT0B ODT0: SDRAMs D[7:4] PCK0A_t PCK0B_t PCK0A_c PCK0B_c CK-t: SDRAMs D[3:0], D8 CK_t: SDRAMs D[7:4] CK_c: SDRAMs D[3:0], D8 CK_c: SDRAMs D[7:4]
CK0_t 120 CK0_c CK1_t CK1_c PAR_IN RESET_n RST_n
120
Err_Out_n RST_n: SDRAMs D[17:0]
Rev. 0.02 / Apr. 2009
13
3.3 4GB, 512Mx72 Module(1Rank of x4)
A[N:O]A /BA[N:O]A A[O:N]B /BA[O:N]B
ZQ
RCASA_n
RS0A_n RRASA_n
RS0B_n RRASB_n
PCK0A_c RCKE0A
RCASB_n
RWEA_n
RODT0A
PCK0B_c RCKE0B
PCK0A_t
RWEB_n
PCK0B_t
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D8
CAS_n WE_n CK_c CKE CK_t ODT
D17
CAS_n WE_n CK_c CKE CK_t ODT
D4
CAS_n WE_n CK_c CKE CK_t ODT
D13
CAS_n WE_n CK_c CKE CK_t ODT ODT ODT ODT
A[N:O]/BA[N:O]
ZQ
VSS
VSS
VSS
RAS_n
RAS_n
RAS_n
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D3
CAS_n WE_n CK_c CKE CK_t ODT
D12
CAS_n WE_n CK_c CKE CK_t ODT
D5
CAS_n WE_n CK_c CKE CK_t ODT
D14
CAS_n WE_n CK_c CKE CK_t
A[N:O]/BA[N:O]
ZQ
VSS
VSS
VSS
RAS_n
RAS_n
RAS_n
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D2
CAS_n WE_n CK_c CKE CK_t ODT
D11
CAS_n WE_n CK_c CKE CK_t ODT
D6
CAS_n WE_n CK_c CKE CK_t ODT
D15
CAS_n WE_n CK_c CKE CK_t
A[N:O]/BA[N:O]
ZQ
VSS
VSS
VSS
RAS_n
RAS_n
RAS_n
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D1
CAS_n WE_n CK_c CKE CK_t ODT
D10
CAS_n WE_n CK_c CKE CK_t ODT
D7
CAS_n WE_n CK_c CKE CK_t ODT
D16
CAS_n WE_n CK_c CKE CK_t
A[N:O]/BA[N:O]
VSS
VSS
VSS
RAS_n
RAS_n
RAS_n
A[N:O]/BA[N:O]
D0
CAS_n WE_n CK_c CKE CK_t ODT
D9
CAS_n WE_n CK_c CKE CK_t ODT
A[N:O]/BA[N:O]
VSS
RAS_n
Vtt
VDDSPD EVENT SCL SDA
VDDSPD EVENT SCL SDA
RAS_n
CS_n
CS_n
SA0
SA0 SA1 SA2 VSS
VSS
DQS0_t DQS0_c VSS DQ[3:0]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS9_t DQS9_c VSS DQ[7:4]
DQS_t DQS_c DM DQ [3:0]
ZQ
Vtt
SPD with SA1 Integrated SA2 TS VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
VDDSPD VDD VTT VREFCA VREFDQ VSS SPD
D0-D17
Note:
1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15 %. 3. See the wiring diagrams for all resistors associated with the command, address and control bus. 4. ZQ resistors are 240 %. For all other resistor values refer to the appropriate wiring diagram.
RAS_n
CS_n
CS_n
CS_n
CS_n
D0-D17 D0-D17 D0-D17
Rev. 0.02 / Apr. 2009
VSS
DQS1_t DQS1_c VSS DQ[11;8]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS10_t DQS10_c VSS DQ[15:12]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS7_t DQS7_c VSS DQ[59:56]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS16_t DQS16_c VSS DQ[63:60]
DQS_t DQS_c DM DQ [3:0]
RAS_n
CS_n
CS_n
CS_n
CS_n
VSS
DQS2_t DQS2_c VSS DQ[19:16]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS11_t DQS11_c VSS DQ23:20]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS6_t DQS6_c VSS DQ[51:48]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS15_t DQS15_c VSS DQ[55;52]
DQS_t DQS_c DM DQ [3:0]
RAS_n
CS_n
CS_n
CS_n
CS_n
VSS
DQS3_t DQS3_c VSS DQ[27:24]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS12_t DQS12_c VSS DQ[31:28]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS5_t DQS5_c VSS DQ[43:40]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS14_t DQS14_c VSS DQ[47:44]
DQS_t DQS_c DM DQ [3:0]
RAS_n
CS_n
CS_n
CS_n
CS_n
VSS
DQS8_t DQS8_c VSS CB[3:0]
DQS_t DQS_c DM DQ [3:0]
ZQ
DQS17_t DQS17_c VSS CB[7:4]
DQS_t DQS_c DM DQ [3:0]
ZQ
RODT0B
DQS4_t DQS4_c VSS DQ[35:32]
DQS_t DQS_c DM DQ [3:0]
DQS13_t DQS13_c VSS DQ[39:36]
DQS_t DQS_c DM DQ [3:0]
ZQ
14
S0_n S1_n BA[2:0] A[15:0] RAS_n CAS_n WE_n CKE[1:0] ODT[1:0]
1:2 R E G I S T E R / P L L
RS0A_n RS1A_n RS0B_n RS1B_n
CS0A_n: SDRAMs D[3:0], D8, D[12:9], D17 CS1A_n: SDRAMs D[21:18], D26, D[30:27], D35 CS0B_n: SDRAMs D[7:4], D[16:13] CS1B_n: SDRAMs D[25:22], D[34:31]
RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RBA[2:0]B BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[15:0]A A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RA[15:0]B A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RRASA_n RAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RRASB_n RAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCASA_n CAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RCASB_n CAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RWEA_n WE_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RWEB_n WE_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A CKE[1:0]A_n: SDRAMs D[3:0], D8. D[12:9], D17 RCKE0B CKE[1:0]B_n: SDRAMs D[21:18], D26, D[30:27], D35 RODT[1:0]A ODT0: SDRAMs D[3:0], D8. D[12:9], D17 RODT[1:0]B ODT0: SDRAMs D[21:18], D26, D[30:27], D35 CK0A_t_R0 CK0B_t_R0 CK0A_t_R1 CK0B_t_R1 CK0A_c_R0 CK0B_c_R0 CK0A_c_R1 CK0B_c_R1 CK-t: SDRAMs D[3:0], D8, D[21:18], D26 CK_t: SDRAMs D[7:4], D[25:22] CK-t: SDRAMs D[12:9], D17, D[30:27], D35 CK_t: SDRAMs D[16:13], D[34:31] CK_c: SDRAMs D[3:0], D8, D[21:18], D26 CK_c: SDRAMs D[7:4], D[25:22] CK_c: SDRAMs D[12:9], D17, D[30:27], D35 CK_c: SDRAMs D[16:13], D[34:31]
CK0_t 120 CK0_c CK1_t CK1_c PAR_IN RESET_n RST_n
120
Err_Out_n RST_n: All SDRAMs
* S[3:2]_n are NC
(Note: Otherwise stated differently all resistors values on this base are 22+-5%)
Rev. 0.02 / Apr. 2009
15
VSS DQS1_t DQS1_c DM1/TDQS10_t TDQS10_c DQ[15:8]
VSS DQS8_t DQS8_c DM8/TDQS17_t TDQS17_c CB[7:0]
VSS DQS2_t DQS2_c DM2/TDQS11_t TDQS11_c DQ[23:16]
VSS DQS3_t DQS3_c DM3/TDQS12_t TDQS12_c DQ[31:24]
VSS DQS0_t DQS0_c DM0/TDQS9_t TDQS9_c DQ[7:0]
Vtt
CS_n CS_n CS_n CS_n
CS_n
RS0_n RRASA_n RCASA_n RWEA_n PCK0A_t
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n WE_n CK_t CK_t CK_t CK_t WE_n WE_n WE_n CAS_n CAS_n CAS_n RAS_n RAS_n RAS_n
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n
Rev. 0.02 / Apr. 2009
CAS_n
WE_n
CK_t
D9
CK_c CK_c CK_c CK_c
D10
D11
D12
D17
CK_c
PCK0A_c RCKE0A RODT0A RA[N:0]A /RBA[N:0]A
CKE ODT A[N:O]/BA[N:0] A[N:O]/BA[N:0] A[N:O]/BA[N:0] A[N:O]/BA[N:0] ODT ODT ODT
CKE
CKE
CKE
CKE
ODT
A[N:O]/BA[N:0]
VSS
VSS
VSS
VSS
VSS
CS_n RAS_n CAS_n WE_n CK_t CK_t CK_t CK_t WE_n WE_n WE_n CAS_n CAS_n CAS_n RAS_n RAS_n RAS_n
CS_n
CS_n
CS_n
CS_n
RS1_n
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n
CAS_n
WE_n
CK_t
D0
CK_c CKE ODT A[N:O]/BA[N:0] A[N:O]/BA[N:0] A[N:O]/BA[N:0] ODT ODT ODT CKE CKE CKE CK_c CK_c CK_c
D1
D2
D3
D8
CK_c
CKE
RCKE1A VDD
ODT
3.4 8GB, 1Gx72 Module(4Rank of x8)
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
VSS
VSS
VSS
VSS
VSS
CS_n RAS_n CAS_n WE_n CK_t CK_t CK_t WE_n WE_n CAS_n CAS_n RAS_n RAS_n
CS_n
CS_n
CS_n
CS_n RAS_n CAS_n WE_n CK_t
RS2_n
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n
CAS_n
WE_n
CK_t
PCK1A_t
D27
CK_c CKE ODT A[N:O]/BA[N:0] A[N:O]/BA[N:0] ODT ODT CKE CKE CK_c CK_c
D28
D29
D30
D35
CK_c
CK_c CKE ODT
PCK1A_c RODT1A
A[N:O]/BA[N:0]
CKE
ODT
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
VSS
VSS
VSS
VSS
VSS
CS_n RAS_n CAS_n WE_n CK_t CK_t WE_n CAS_n RAS_n
CS_n
CS_n
CS_n RAS_n CAS_n WE_n CK_t
CS_n RAS_n CAS_n WE_n CK_t
RS3_n
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n
CAS_n
WE_n
CK_t
D18
CK_c CKE ODT A[N:O]/BA[N:0] CKE ODT CK_c
D19
D20
D21
D26
CK_c
CK_c CKE ODT
CK_c CKE ODT
CKE
ODT
VDD
A[N:O]/BA[N:0] A[N:O]/BA[N:0] A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
16
/RBA[N:0]A
RRASA_n
RCASA_n
RA[N:0]A
PCK0A_c
PCK1A_c
RWEA_n
PCK0A_t
PCK1A_t
RODT0A
RS1_n
RS2_n
RODT1A
RCKE0A
RCKE1A
RS0_n
RS3_n
VDD
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
D13
WE_n CK_c CK_t ODT CKE
D4
WE_n CK_c CK_t ODT CKE
D31
WE_n CK_c CK_t ODT CKE
D22
WE_n CK_c CK_t ODT ODT ODT ODT CKE CKE CKE CKE
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
D14
WE_n CK_c CK_t ODT CKE
D5
WE_n CK_c CK_t ODT CKE
D32
WE_n CK_c CK_t ODT CKE
D23
WE_n CK_c CK_t
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
D15
WE_n CK_c CK_t ODT CKE
D6
WE_n CK_c CK_t ODT CKE
D33
WE_n CK_c CK_t ODT CKE
D24
WE_n CK_c CK_t
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
A[N:O]/BA[N:0]
D16
WE_n CK_c CK_t ODT CKE
D7
WE_n CK_c CK_t ODT CKE
D34
WE_n CK_c CK_t ODT CKE
D25
WE_n CK_c CK_t
Vtt
VDDSPD EVENT SCL SDA
Note:
VDDSPD
SA0
SA0 SA1 SA2 VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
VDDSPD VDD VTT VREFCA VREFDQ VSS Serial PD
D0-D35
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15 %. 3. See the wiring diagrams for all resistors associated with the command, address and control bus. 4. ZQ resistors are 240 %. For all other resistor values refer to the appropriate wiring diagram.
A[N:O]/BA[N:0]
VSS DQS7_t DQS7_c DM7/TDQS16_t TDQS16_c DQ[63:56]
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
A[N:O]/BA[N:0]
VSS DQS6_t DQS6_c DM6/TDQS15_t TDQS15_c DQ[55:48]
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
A[N:O]/BA[N:0]
VSS DQS5_t DQS5_c DM5/TDQS14_t TDQS14_c DQ[47:40]
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
A[N:O]/BA[N:0]
VSS DQS4_t DQS4_c DM4/TDQS13_t TDQS13_c DQ[39:32]
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VSS
ZQ DQS DQS TDQS TDQS DQ [7:0]
RAS_n CAS_n CS_n
VDD
D0-D35 D0-D35 D0-D35
Rev. 0.02 / Apr. 2009
17
S0_n S1_n S2_n S3_n BA[N:0] A[N:0] RAS_n CAS_n WE_n CKE0 CKE1 ODT0 ODT1 CK0_t
120
1:2 R E G I S T E R / P L L
CK0_c CK1_t CK1_c PAR_IN RESET_n RST_n
120
RS0_n CS1_n: SDRAMs D[17:9] RS1_n CS0_n: SDRAMs D[8:0] RS2_n CS1_n: SDRAMs D[35:27] RS3_n CS0_n: SDRAMs D[26:18] RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[N:0]B BA[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RA[N:0]A A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 A[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RA[N:0]B RRASA_n RAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RRASB_n RAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RCASA_n CAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RCASB_n CAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RWEA_n WE_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RWEB_n WE_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RCKE0A CKE1: SDRAMs D[12:9], D17, D[30:27], D35 RCKE0B CKE1: SDRAMs D[16:13], D[34:31] RCKE1A CKE0: SDRAMs D[3:0], D8, D[21:18], D26 RCKE1B CKE0: SDRAMs D[7:4], D[25:22] RODT0A ODT1: SDRAMs D[12:9], D17 RODT0B ODT1: SDRAMs D[16:13] RODT1A ODT1: SDRAMs D[30:27], D35 RODT1B ODT1: SDRAMs D[34:31] PCK0A_t CK_t: SDRAMs D[3:0], D[12:8], D17 PCK0B_t CK_t: SDRAMs D[7:4], D[16:13] PCK1A_t CK_t: SDRAMs D[21:18], D[30:26], D35 PCK1B_t CK_t: SDRAMs D[25:22], D[34:31] PCK0A_c CK_c: SDRAMs D[3:0], D[12:8], D17 PCK0B_c CK_c: SDRAMs D[7:4], D[16:13] PCK1A_c CK_c: SDRAMs D[21:18], D[30:26], D35 PCK1B_c CK_c: SDRAMs D[25:22], D[34:31] Err_Out_n RESET_n: SDRAMs D[35:0]
Rev. 0.02 / Apr. 2009
18
3.5 8GB, 1Gx72 Module(2Rank of x4)
VSS RS0_n RS1_n
DM CS_n ZQ DQS0_t DQS0_c DQ[3:0] DQS_t DQS_c DQ [3:0] VSS DQS_t DQS_c DQ [3:0] DM CS_n ZQ VSS DQS9_t DQS9_c DQ[7:4] DQS_t DQS_c DQ [3:0] DM CS_n ZQ VSS DQS_t DQS_c DQ [3:0] DM CS_n ZQ VSS
D0
D18
D9
D27
DM CS_n ZQ DQS1_t DQS1_c DQ[11:8] DQS_t DQS_c DQ [3:0]
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS10_t DQS10_c DQ[12:15] DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS
D1
D19
D10
D28
DM CS_n ZQ DQS2_t DQS2_c DQ[16:19] DQS_t DQS_c DQ [3:0]
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS11_t DQS11_c DQ[20:23] DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS
D2
D20
D11
D29
DM CS_n ZQ DQS3_t DQS3_c DQ[24:27] DQS_t DQS_c DQ [3:0]
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS12_t DQS12_c DQ[28:31] DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS
D3
D21
D12
D30
DM CS_n ZQ DQS4_t DQS4_c DQ[32:35] DQS_t DQS_c DQ [3:0]
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS13_t DQS13_c DQ[36:39] DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS
D4
D22
D13
D31
DM CS_n ZQ DQS5_t DQS5_c DQ[40:43] DQS_t DQS_c DQ [3:0]
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS14_t DQS14_c DQ[44:47] DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS
D5
D23
D14
D32
DM CS_n ZQ DQS6_t DQS6_c DQ[48:51] DQS_t DQS_c DQ [3:0]
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS15_t DQS15_c DQ[52:55] DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS
D6
D24
D15
D33
DM CS_n ZQ DQS7_t DQS7_c DQ[56:59] DQS_t DQS_c DQ [3:0]
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS16_t DQS16_c DQ[60:63] DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS
D7
D25
D16
D34
DM CS_n ZQ DQS8_t DQS8_c CB[3:0] DQS_t DQS_c DQ [3:0]
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS17_t DQS17_c CB[7:4] DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS DQS_t DQS_c DQ [3:0]
DM CS_n ZQ
VSS
D8
D26
D17
D35
VDDSPD
VDDSPD VDDSPD SA0 SA0 SA1 SA2 VSS
SPD
D0-D17
VDD VTT VREFCA VREFDQ VSS
EVENT
SCL SDA
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
D0-D17 D0-D17 D0-D17
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
Note: 1. DQ-to-I/O wiring may be changed within a nibble. 2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
Rev. 0.02 / Apr. 2009
19
S0_n S1_n S2_n S3_n BA[N:0] A[N:0] RAS_n CAS_n WE_n CKE0 CKE1 ODT0 ODT1 CK0_t
120
1:2 R E G I S T E R / P L L
CK0_c CK1_t CK1_c PAR_IN RESET_n RST_n
120
RS0_n CS1_n: SDRAMs D[17:9] RS1_n CS0_n: SDRAMs D[8:0] RS2_n CS1_n: SDRAMs D[35:27] RS3_n CS0_n: SDRAMs D[26:18] RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[N:0]B BA[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RA[N:0]A A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 A[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RA[N:0]B RRASA_n RAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RRASB_n RAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RCASA_n CAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RCASB_n CAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RWEA_n WE_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RWEB_n WE_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RCKE0A CKE1: SDRAMs D[12:9], D17, D[30:27], D35 RCKE0B CKE1: SDRAMs D[16:13], D[34:31] RCKE1A CKE0: SDRAMs D[3:0], D8, D[21:18], D26 RCKE1B CKE0: SDRAMs D[7:4], D[25:22] RODT0A ODT1: SDRAMs D[12:9], D17 RODT0B ODT1: SDRAMs D[16:13] RODT1A ODT1: SDRAMs D[30:27], D35 RODT1B ODT1: SDRAMs D[34:31] PCK0A_t CK_t: SDRAMs D[3:0], D[12:8], D17 PCK0B_t CK_t: SDRAMs D[7:4], D[16:13] PCK1A_t CK_t: SDRAMs D[21:18], D[30:26], D35 PCK1B_t CK_t: SDRAMs D[25:22], D[34:31] PCK0A_c CK_c: SDRAMs D[3:0], D[12:8], D17 PCK0B_c CK_c: SDRAMs D[7:4], D[16:13] PCK1A_c CK_c: SDRAMs D[21:18], D[30:26], D35 PCK1B_c CK_c: SDRAMs D[25:22], D[34:31] Err_Out_n RESET_n: SDRAMs D[35:0]
Rev. 0.02 / Apr. 2009
20
4. Pin Capacitance (VDD=1.5V, VDDQ=1.5V)
2GB: HMT325V7AFR8C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
4GB: HMT351V7AFR8C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
4GB: HMT351V7AFR4C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
8GB: HMT41GV7AMR8C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
8GB: HMT41GV7AMR4C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Note: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only.
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
Rev. 0.02 / Apr. 2009
21
5. IDD Specifications(Tcase: 0 to 95oC)
2GB, 256M x 72 R-DIMM: HMT325V7AFR8C Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3 1066 1439 1529 1169 1214 336 498 1169 1259 543 2024 2069 2654 336 363 363 2654 DDR3 1333 1484 1574 1214 1259 336 543 1214 1304 543 2159 2204 2654 336 363 363 2834 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
4GB, 512M x 72 R-DIMM: HMT351V7AFR8C Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3 1066 1844 1934 1574 1664 444 768 1574 1754 858 2429 2474 3059 444 498 498 3059 DDR3 1333 1934 2024 1664 1754 444 858 1664 1844 858 2609 2654 3104 444 498 498 3284 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 0.02 / Apr. 2009
22
4GB, 512M x 72 R-DIMM: HMT351V7AFR4C Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 1066 2114 2294 1574 1664 444 768 1574 1754 858 3284 3374 4544 444 498 498 4554 DDR3 1333 2204 2384 1664 1754 444 858 1664 1844 858 3554 3644 4544 444 498 498 4904 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
8GB, 1D x 72 R-DIMM: HMT41GR7AMR8C Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 1066 2654 2744 2384 2564 660 1308 2384 2744 1488 3239 3284 3869 660 768 768 3869 DDR3 1333 2834 2924 2564 2744 660 1488 2564 2924 1488 3509 3554 4004 660 768 768 4184 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 0.02 / Apr. 2009
23
8GB, 1G x 72 R-DIMM: HMT41GV7AMR4C Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 1066 2924 3104 2384 2564 660 1308 2384 2744 1488 4094 4184 5354 660 768 768 5354 DDR3 1333 3104 3284 2564 2744 660 1488 2564 2924 1488 4454 4544 5444 660 768 768 5804 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 0.02 / Apr. 2009
24
6. Dimm Outline Diagram
6.1 256Mx72 - HMT325V7AFR8C
Front
2.10 0.15 14.90
Detail C
3 0.1
13.60
18.75
0.15
Registering Clock Driver
15.80
0.1
3
0.1
1
120
8.00
0.1
2X3.0
0.10
5.175
47.00
Detail A
Detail B
128.95 133.35
71.00
Back
240
SPD/TS
121
Side
Detail of Contacts A
0.80 0.05
Detail of Contacts B
2.50
Detail of Contacts C
3.65mm max
14.90 0.4
0.20
0.20
2.50
0.3~0.1
1.00
1.50
0.10
6.2 512Mx72 - HMT351V7AFR8C
5.00
2.50
6.2 256Mx72 - HMT125V7BFR8C
0.20
3.80
0.3
0.15
13.60
1.27 max
mm
Rev. 0.02 / Apr. 2009
25
Front
2.10 0.15 14.90
Detail C
3 0.1
13.60
18.75
0.15
Registering Clock Driver
15.80
0.1
3
0.1
1
120
8.00
0.1
2X3.0
0.10
5.175
47.00
Detail A
Detail B
128.95 133.35
71.00
Back
240
SPD/TS
121
Side
Detail of Contacts A
0.80 0.05
Detail of Contacts B
2.50
Detail of Contacts C
3.65mm max
14.90 0.4
0.20
0.20
0.20
3.80
0.3
0.15
13.60
2.50
0.3~0.1
6.3 512Mx72 - HMT351V7AFR4C
5.00
1.00
1.50
0.10
2.50
1.27 max
mm
Rev. 0.02 / Apr. 2009
26
Front
2.10 0.15 14.90
Detail C
3 0.1
13.60
18.75
0.15
Registering Clock Driver
15.80
0.1
3
0.1
1
120
8.00
0.1
2X3.0
0.10
5.175
47.00
Detail A
Detail B
128.95 133.35
71.00
Back
240
SPD/TS
121
Side
Detail of Contacts A
0.80 0.05
Detail of Contacts B
2.50
Detail of Contacts C
3.65mm max
14.90 0.4
0.20
0.20
0.20
3.80
0.3
0.15
13.60
2.50
0.3~0.1
1.00
1.50
0.10
5.00
2.50
1.27 max
mm
Rev. 0.02 / Apr. 2009
27
6.4 1Gx72 - HMT41GV7AMR8C
Front
2.10 0.15 14.90
Detail C
3 0.1
13.60
18.75
0.15
Registering Clock Driver
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
3
0.1
1
DDP
15.80
0.1
120
8.00
0.1
2X3.0
0.10
5.175
47.00
Detail A
Detail B
128.95 133.35
71.00
Back
SPD/TS
DDP
DDP
DDP
DDP
DDP
DDP
DDP
240
DDP
DDP
121
Detail of Contacts A
0.80 0.05
Detail of Contacts B
2.50
Detail of Contacts C
Side
3.95mm max
14.90 0.4
0.20
0.20
0.20
3.80
0.3
0.15
13.60
2.50
0.3~0.1
1.00
1.50
0.10
2.50
5.00
1.27 max
mm
Rev. 0.02 / Apr. 2009
28
6.4 512Mx72 - HMT41GV7AMR4C (Heat Sink)
Front
36.58 36.58 18.75 0.15
12.3 13.3
SPD/TS
DDP
1
DDP
DDP
DDP
DDP
SPD/TS
DDP
DDP
DDP
DDP
240
DDP
121
Detail of Contacts A
0.80 0.05
0.15
0.20
0.20
3.80
0.3
2.50
0.3~0.1
1.00
1.50
0.10
2.50
0.20
Rev. 0.02 / Apr. 2009
DDP
DDP
DDP
Detail of Contacts B
2.50
DDP
5.00
DDP
DDP
DDP
DDP
120
126.8
Back
Detail of Contacts C
Side
9.35mm max
14.90 0.4 13.60
2.15mm 1.27 max mm
29
6.4 1Gx72 - HMT41GV7AMR8C
Front
52.9 2.10 0.15 9.8 3 0.1 6.3 9.8 0.10 2.1 5.3
Detail C
18.75 0.15
Registering Clock Driver
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
3
0.1
1
DDP
15.80
0.1
120
8.00
0.1
2X3.0
0.10
5.175
47.00
Detail A
Detail B
128.95 133.35
71.00
Back
SPD/TS
DDP
DDP
DDP
DDP
DDP
DDP
DDP
240
DDP
DDP
121
Detail of Contacts A
0.80 0.05
Detail of Contacts B
2.50
Detail of Contacts C
Side
3.95mm max
9.8 0.4
0.20
0.20
0.20
3.80
0.3
0.15
8.5
2.50
0.3~0.1
1.00
1.50
0.10
2.50
5.00
1.27 max
mm
Rev. 0.02 / Apr. 2009
30
6.4 512Mx72 - HMT351V7AMP4C (Heat Spreader)
Front
29 29 18.75 0.15
12.3 13.3
DDP
1
DDP DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
127
Back
SPD/TS
120
DDP
DDP
DDP
DDP
DDP
DDP
DDP
240
SPD/TS
DDP
121
Detail of Contacts A
0.80 0.05
Detail of Contacts B
2.50
Detail of Contacts C
Side
7.4mm max
9.8 0.4
0.20
0.20
0.20
3.80
0.3
0.15
8.5
2.50
0.3~0.1
1.00
1.50
0.10
2.50
6.2mm 1.27 max mm
5.00
Rev. 0.02 / Apr. 2009
31
6.5 1Gx72 - HMT41GV7AMR4C
Front
2.10 0.15 14.90
Detail C
3 0.1
13.60
18.75
0.15
Registering Clock Driver
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
3
0.1
1
DDP
15.80
0.1
120
8.00
0.1
2X3.0
0.10
5.175
47.00
Detail A
Detail B
128.95 133.35
71.00
Back
DDP
DDP
DDP
DDP
SPD/TS
DDP
DDP
DDP
DDP
240
DDP
121
Detail of Contacts A
0.80 0.05
Detail of Contacts B
2.50
Detail of Contacts C
Side
3.95mm max
14.90 0.4
0.20
0.20
0.20
3.80
0.3
0.15
13.60
2.50
0.3~0.1
1.00
1.50
0.10
2.50
5.00
1.27 max
mm
Rev. 0.02 / Apr. 2009
32
6.5 1Gx72 - HMT41GV7AMR4C (Heat Sink)
Front
36.58 36.58 18.75 0.15
12.3 13.3
SPD/TS
DDP
1
DDP
DDP
DDP
DDP
SPD/TS
DDP
DDP
DDP
DDP
240
DDP
121
Detail of Contacts A
0.80 0.05
0.15
0.20
0.20
3.80
0.3
2.50
0.3~0.1
1.00
1.50
0.10
2.50
0.20
Rev. 0.02 / Apr. 2009
DDP
DDP
DDP
Detail of Contacts B
2.50
DDP
5.00
DDP
DDP
DDP
DDP
120
126.8
Back
Detail of Contacts C
Side
9.35mm max
14.90 0.4 13.60
2.15mm 1.27 max mm
33
6.5 1Gx72 - HMT41GV7AMR4C
Front
52.9 2.10 0.15 9.8 3 0.1 6.3 9.8 0.10 2.1 5.3
Detail C
18.75 0.15
Registering Clock Driver
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
3
0.1
1
DDP
15.80
0.1
120
8.00
0.1
2X3.0
0.10
5.175
47.00
Detail A
Detail B
128.95 133.35
71.00
Back
SPD/TS
DDP
DDP
DDP
DDP
DDP
DDP
DDP
240
DDP
DDP
121
Detail of Contacts A
0.80 0.05
Detail of Contacts B
2.50
Detail of Contacts C
Side
3.95mm max
9.8 0.4
0.20
0.20
0.20
3.80
0.3
0.15
8.5
2.50
0.3~0.1
1.00
1.50
0.10
2.50
5.00
1.27 max
mm
Rev. 0.02 / Apr. 2009
34
6.5 1Gx72 - HMT41GV7AMR4C (Heat Spreader)
Front
29 29 18.75 0.15
12.3 13.3
DDP
1
DDP DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
127
Back
SPD/TS
120
DDP
DDP
DDP
DDP
DDP
DDP
DDP
240
SPD/TS
DDP
121
Detail of Contacts A
0.80 0.05
Detail of Contacts B
2.50
Detail of Contacts C
Side
7.4mm max
9.8 0.4
0.20
0.20
0.20
3.80
0.3
0.15
8.5
2.50
0.3~0.1
1.00
1.50
0.10
2.50
6.2mm 1.27 max mm
5.00
Rev. 0.02 / Apr. 2009
35

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